Silicon-on-insulator (SOI) technology is becoming of increasing importance in the field of integrated circuits. SOI technology deals with the formation of transistors in a layer of semiconductor material that overlies an insulating layer. A common embodiment of SOI structures is a single crystal layer of silicon that overlies a layer of silicon dioxide.
High performance and high-density integrated circuits are generally achievable using SOI technology because of the reduction of parasitic elements present in integrated circuits formed in bulk semiconductor. For example, for a MOS transistor formed in bulk, parasitic capacitance is present at the junction between the source/drain regions and the underlying substrate, and the possibility of breakdown of the junction between source/drain regions and the substrate regions also exists. A further example of parasitic elements is present for CMOS technology in bulk, where parasitic bipolar transistors formed by n-channel and p-channel transistors in adjacent wells can give rise to latch-up problems. Since SOI structures significantly alleviate parasitic elements, and increase the junction breakdown tolerance of the structure, the SOI technology is well suited for high performance (e.g., analog devices) and high-density integrated circuits.
However, the underlying insulator film in an SOI structure presents certain problems relative to the transistor performance. For instance, noise and coupling capacitance associated with the SOI structure tends to degrade the transistor performance. In an attempt to reduce or alleviate the aforementioned noise and coupling capacitance issues, the industry uses a backside wafer contact. Unfortunately, the backside wafer contact currently employed uses costly lead frames and/or down bonding techniques that are typically relegated to the transistor die perimeter.
Accordingly, what is needed is a backside contact and method for manufacture therefore that does not experience the drawbacks of the conventional backside contacts.